Project Overview
Project Overview
This project involved the implementation of a highly complex, multi-hierarchical SoC on TSMC 40G technology, featuring a large die size, significant transistor density, multiple power islands, and intricate clocking architecture. The design demanded precise floor planning, power optimization, advanced clock-tree engineering, and flip-chip packaging support—making it one of the most challenging integration tasks in the program.
Key Achievements
Key Silicon Specifications
Die Area: ~86 mm² (post-shrink)
Total Instances: 20M+ standard-cell and macro instances
Transistor Count: Over 500 million
On-chip Memory: 20 MB+ SRAM
Metal Stack: 11 metal layers (5×2×2 stack-up + RDL)
Process Technology: TSMC 40G, supporting 0.9V and 1.8V operations
Package & Bump Architecture
Flip-Chip Die Support: 150 µm bump pitch
BGA Configurations:
0.8 mm ball pitch in 23×23 FCBGA
0.5 mm pitch in 14×14 POP (Package-on-Package)
Designed for high-reliability board attach and multi-stack packaging environments.
Multi-Hierarchical SoC Integration
1. Power & Voltage Architecture
28 independent power islands, enabling fine-grained power gating and dynamic power management.
3 different core supply voltages, supporting performance and leakage optimization across sub-systems.
Multi-Vt libraries used extensively to balance speed, leakage, and area efficiency.
2. Clocking Strategy
Built and optimized 100+ clock trees, addressing:
Multi-frequency domains
Scan and test clocks
Cross-domain timing closure
Ensured low skew, consistent insertion delays, and multi-corner timing robustness.
3. Advanced IO and Routing Constraints
150 µm bump pitch and 30 µm IO pitch required careful pad-ring design, redistribution layer planning, and bump-to-pad alignment.
Ensured seamless integration with flip-chip packaging constraints.
4. Design Protections & Reliability
Full integration of ESD networks to meet pad-ring and IP-level protection requirements.
CSR (Chip System Reliability) elements embedded to meet long-term reliability and electromigration targets.
Summary of Capabilities Demonstrated
Successfully handled a massive SoC with half a billion transistors.
Delivered tight integration across multiple voltage domains and power islands.
Achieved reliable clock distribution with 100+ optimized trees.
Enabled advanced flip-chip packaging with fine-pitch bumps and dense IO requirements.
Ensured design robustness through full inclusion of ESD and reliability features.