Key Specifications

• Technology Node: 28nm (TSMC)

• Chip Dimensions: 4.5 mm × 5.535 mm

• Team Size: 5 Physical Design Engineers

• Primary Tool: Cadence Innovus Implementation System

• Scope: Complete Turnkey PD — Netlist to GDSII

• Target Application: High-performance Networking Chip

• Operating Frequency: 700 MHz

• Integrated Analog IPs: PLL, DDR PHY, SERDES blocks

• Design Approach: Flat chip architecture

Major Features & Technical Highlights

1. Clocking Complexity

The design contained 10 independent clocks, including scan clocks, requiring:

• Careful CTS planning

• Clock skew and insertion delay optimization

• Multi-domain timing analysis and cleanup

2. Congestion Management & Area Optimization

Reducing routing congestion and meeting area targets was a significant challenge due to:

• Analog IP placement constraints

• High standard-cell density

• Flat implementation approach

The team optimized placement, routing layers, blockages, and pin assignment to achieve a clean layout within the required die size.

3. Timing Closure Across All TSMC Signoff Corners

Complete timing closure was achieved across:

• All PVT corners

• Functional, test, and scan modes

• Setup, hold, and clock-gating checks

This ensured robust performance for silicon across all operating conditions.

Final Outcome

• Successful delivery of GDSII with full signoff compliance

• Achieved 700 MHz performance target

• Completed routing and timing closure without violating congestion thresholds

• Managed complex analog IP integration in a flat physical design flow

• Demonstrated strong teamwork and efficient execution with a compact 5-engineer team