Project Overview
Key Challenges
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Rapidly evolving architecture impacting DV environment
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Multi-core boot and interaction validation
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Analog IP availability during product cycle
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Gate-Level Simulation (GLS) bring-up
Key Achievements
Contributions:-
Defined verification objectives and built DV environment from scratch
Developed Constrained-Random IP-level testbenches
Implemented checkers: Scoreboards, Assertions, Jasper setups, connectivity and end-to-end data checks
Achieved 100% toggle coverage and closed all bugs
Outcome: Delivered 3 successful tape-outs