Project Overview
Team: 10 Layout & Design Engineers – AIONSI
Scope: Complete Analog Layout, Extraction Migration, and Physical Verification
Project Overview
AIONSI executed a turnkey analog layout and design initiative focused on developing a high-performance analog front-end solution aimed at improving the signal quality and efficiency of advanced electronic systems. The project centered around improving noise performance, strengthening signal conditioning, and reducing overall system complexity in analog-based architectures.
The solution integrated a Low-Noise Transconductance Amplifier (LNTA) and ADC blocks, forming a tightly coupled analog front end suitable for next-generation low-power applications. The team led the full layout cycle—from migration of extraction methodologies to physical verification—while meeting stringent area, technology, and performance constraints.
Key Achievements
Key Technical Work
Migration from LPE → LXP Extraction Flow
The project required transitioning from a traditional Layout Parasitic Extraction (LPE) methodology to a more advanced Layout Extraction Process (LXP). This shift brought higher extraction accuracy and better modeling of analog parasitics but demanded careful handling due to its complexity.
AIONSI successfully restructured the extraction flow, validated models, and ensured consistency across all design stages.
Comprehensive Physical Verification Execution
After completing the migration, the team performed full physical verification, including:
Design Rule Check (DRC)
Layout vs. Schematic (LVS)
Antenna checks
Design for Manufacturability (DFM)
These checks ensured that the final analog layout was both functionally correct and manufacturable without issues.
Pilot Layout Details
The pilot circuit was part of a memory block, consisting of:
Level shifters
Buffers
Power switches
Additional support logic
Technology: TSMC 22ULL (22nm)
Functional Blocks: 14 blocks with ~20 instances
Transistor Count: ~4,800 devices (mix of 0.8V / 2.5V / 3.3V MOSFETs)
Final Layout Area: ~4,500 µm² (82 µm × 55 µm)
The design was delivered DRC-clean and LVS-clean, meeting all foundry requirements.
Challenges & Resolutions
1. Routing Complexity Due to Blockages and Boundary Limits
The layout encountered routing difficulties because of strict metal routing boundaries and blockages. These constraints limited optimization and area savings.
Despite this, the team optimized path routing layer-by-layer and completed the end layout within the required area target.
2. Tight Area Constraints
The required analog front-end area target left minimal headroom for transistor placement and routing channels. Through repeated refinement and placement optimization, the final layout met the exact area budget without compromising performance.
Final Outcome
Delivered a complete turnkey analog layout solution for an LNTA + ADC-based analog front end.
Fully clean DRC and LVS signoff.
Successful migration to a modern LXP-based extraction methodology.
Optimized within strict area limits, despite routing blockages.
Validated on TSMC 22ULL, ensuring readiness for full-chip integration.