Careers

Experience: 5+ years
Location: Bangalore, India / Sweden
Employment Type: Full-time

Job Summary

We are seeking a highly skilled Senior/Lead ASIC Verification Engineer to contribute to and drive the verification of complex SoC/ASIC designs. The ideal candidate will have strong hands-on experience in SystemVerilog/UVM-based verification environments and a deep understanding of digital design. This role involves leading verification planning, execution, and closure activities, while working closely with cross-functional teams across global development sites.

Key Responsibilities

Required Skills

Preferred Qualifications

• Lead IP/Sub-system/SoC-level verification activities from test plan creation to verification sign-off.
• Develop UVM-based testbenches including agents, sequences, monitors, scoreboards, and coverage components.
• Create, enhance, and maintain constrained-random and directed test scenarios.
• Analyze coverage metrics (functional, code, assertions) to ensure verification completeness.
• Debug complex RTL and testbench issues using simulation tools and waveform debugging.
• Collaborate with RTL designers, architects, firmware, and validation teams across Bangalore/Sweden offices.
• Drive continuous improvements in verification methodology, automation, and workflows.
• Mentor junior engineers and conduct technical reviews of testbench code and verification deliverables.
• (Lead role) Own verification planning, schedule tracking, reporting, and stakeholder communication.

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 5+ years of ASIC/SoC verification experience.
• Strong proficiency in SystemVerilog, UVM, and object-oriented verification environments.
• Solid understanding of digital design fundamentals and SoC architecture.
• Hands-on experience with simulation tools (VCS / Xcelium / Questa) and waveform debug tools.
• Experience with coverage-driven verification (functional, code, assertion) and closure strategies.
• Proficiency in scripting languages (Python / Perl / Shell) for automation and regression infrastructure.

• Experience verifying standard protocols (AXI/ACE/PCIe/DDR/NoC, etc.).
• Knowledge of formal verification (SVA, Jasper/VC Formal).
• Experience with SoC integration verification and low-power verification concepts.
• Exposure to emulation (Veloce, Palladium) or FPGA prototyping platforms.
• Prior experience leading verification teams or owning sub-system level verification closure.
• Experience working in distributed teams across India / Europe is a plus.