RTL Design
- Development of design Spec from system requirements.
- RTL development
- RTL Design of IPs and reusing them in System integration.
- Power Estimation and low power design.
- Clock Domain Crossing (CDC) checks, Linting, equivalence checks
- Code coverage Analysis
- Timely languages VHDL, Verilog, SV and un-timely languages SystemC, C or C++ for design.
Design Verification
- Writing Verification Spec and verification plan from requirement
- Developing verification Environment using SV/UVM, Specman
- SoC level verification using SV/UVM, C
- Processor verification using C language
- Assertion based verification and Formal verification using Jasper Gold
- Functional Coverage Analysis
DFT
- Stuck at Faults Modeling
- Automatically Generating Test Patterns
- Internal Full Scan
- Boundary Scan – JTAG
- BIST - Built In Self Test
- DFT Design Rule Check
PD and Layout
- Floor and power planning
- Placement and routing
- IR, Power and timing analysis
- Clock tree synthesis
- Skew minimization
- Signal integrity (EM) fix and analysis
- Static timing analysis (STA)
- DFM – redundant vias, metal density
- Layout – chip finishing
- Physical verification – DRC/LVS
Embedded Automotive Testing
- Writing Verification Spec and verification plan from requirement
- Manual and Automation Testing
- Developing verification Environment using Merlin, Dspace
- Functional Testing with Vector tools
LAMP Hub