RISC-V Processor Core Family
AionSi processor portfolio spanning embedded through performance and multi-core cluster tiers, with RV32/RV64 support and AXI/CHI integration.
Why an IP portfolio strengthens SoC engineering credibility.
This page presents approved technical material associated with the AionSi engineering capability.
Technical values and verification statements are limited to the supplied source material; customer attribution and additional performance claims are not implied.
What the architecture enables.
The supplied portfolio spans processor cores, coherent/non-coherent interconnect, high-speed I/O and memory controllers that can form major building blocks of heterogeneous SoC architectures.
Show reusable IP depth
The portfolio provides concrete technical evidence across processor, interconnect, memory and high-speed protocol building blocks.
Demonstrate subsystem integration
AXI/CHI interfaces and configurable architectures connect the individual IP blocks into broader SoC integration patterns.
Cover compute and AI memory paths
RISC-V, DDR and HBM evidence provides a credible technical path from compute cores to high-bandwidth memory subsystems.
Strengthen customer technical discussions
Each portfolio item can be reviewed as a focused technical reference rather than relying only on generic capability claims.
SoC engineering where reusable IP meets integration.
AionSi can position the supplied IP portfolio as evidence for SoC architecture, subsystem integration, verification and engineering workstream discussions.
Processor IP
RISC-V portfolio covering embedded, edge-AI, performance and multi-core cluster configurations with AXI/CHI integration.
Interconnect IP
AMBA CHI/AXI fabrics covering coherency, QoS, configurable topology, monitoring and heterogeneous compute connectivity.
Memory IP
DDR4/DDR5 and HBM2e/HBM3 controller portfolios covering scheduling, ECC, refresh, thermal and multi-client behavior.
High-speed protocol IP
PCIe Gen6 and USB 3.x/USB4 controller portfolios covering link management, error recovery, power and protocol integration.
A portfolio that maps to subsystem and SoC programs.
The evidence can be used in customer discussions at IP, subsystem and SoC levels, while keeping each technical claim tied to its supplied portfolio source.
IP families supplied
RISC-V, AMBA, PCIe, DDR, HBM and USB technical portfolio references.
Compute
Embedded through performance and cluster processor configurations.
Memory
DDR and HBM controller evidence for mainstream and AI/HPC memory paths.
Connectivity
PCIe and USB high-speed interface controller evidence.
AionSi Engineering Evidence — RISC-V Processor Core Family
Get the detailed AionSi SoC & IP Engineering reference architecture, implementation flow and engineering methodology.
Have an IP or SoC integration requirement?
Use the supplied IP portfolio as the starting technical evidence for an architecture, subsystem, verification or SoC engineering discussion.