01
Semiconductor-first work
Build expertise around real silicon engineering disciplines and development flows.
Build the engineering behind the next generation of silicon.
AionSi is building an engineering organization for complex semiconductor programs across verification, physical design, RTL, DFT, protocol engineering and SoC integration.
Work on technically demanding silicon problems with ownership, disciplined engineering practices and opportunities to grow across the semiconductor lifecycle.
Engineering depth. Technical ownership. Continuous learning.
Join a semiconductor-focused team where the work is grounded in engineering problems rather than generic technology delivery.
02
Technical ownership
Take responsibility for defined workstreams, engineering decisions and deliverables.
03
Cross-lifecycle exposure
Learn how IP, verification, implementation, DFT and SoC integration connect.
04
Growth with experienced teams
Develop engineering depth through structured execution, reviews and collaboration.
Deep engineering, not generic delivery.
Our teams work across verification, implementation, test and system integration.
01
RTL / IP Design
Microarchitecture, RTL development and design integration.
02
Design Verification
SystemVerilog, UVM, assertions, coverage and verification closure.
03
Physical Design
Implementation, timing, congestion, physical verification and sign-off.
04
DFT
Test architecture, scan, ATPG and manufacturing-test readiness.
05
Protocol Verification
PCIe, USB, DDR, HBM and AMBA interface verification.
06
SoC & IP Engineering
Processor, interconnect, memory, protocol IP and SoC integration.
Current engineering opportunities.
These roles reflect the current approved hiring requirements. AionSi may update openings as the engineering roadmap evolves.
10+ years
SoC DV Manager
Hyderabad
Lead SoC design verification programs with strong team leadership, verification strategy and delivery ownership.
CORE RESPONSIBILITIES
- Lead SoC design verification strategy, execution and closure.
- Own verification planning, technical reviews, debug and delivery milestones.
- Build and mentor a strong design verification engineering team.
REQUIRED / PREFERRED
SoC Design VerificationSystemVerilog / UVMTechnical LeadershipVerification Closure
3+ years
Emulation Engineer
Hyderabad
Join the emulation team to develop, debug and execute complex SoC emulation flows.
CORE RESPONSIBILITIES
- Work on SoC emulation environments and execution flows.
- Debug emulation failures and collaborate with design and verification teams.
- Contribute to reliable emulation bring-up and execution methodology.
REQUIRED / PREFERRED
EmulationSoC VerificationDebugSemiconductor Design Flows
2–5 years
Digital Marketing Executive
Bengaluru
Build digital visibility and demand-generation programs for AionSi in the semiconductor technology market.
CORE RESPONSIBILITIES
- Execute digital marketing programs across relevant channels.
- Create and coordinate semiconductor-focused content and campaigns.
- Support lead generation, analytics and campaign performance tracking.
REQUIRED / PREFERRED
Digital MarketingB2B Technology MarketingContent & CampaignsSemiconductor / Technology
5–8 years
Physical Verification Engineer
Bengaluru and Hyderabad
Own sign-off physical verification for advanced-node designs and ensure tape-out-ready quality.
CORE RESPONSIBILITIES
- Perform DRC, LVS and ERC verification for advanced technology nodes.
- Drive physical sign-off checks and closure toward tape-out.
- Work closely with design, layout and foundry teams to resolve verification issues.
REQUIRED / PREFERRED
DRCLVSERCPhysical Sign-offAdvanced Technology Nodes
5+ years
DV Engineer
Bengaluru
Develop and debug UVM-based verification environments and drive regression and coverage closure.
CORE RESPONSIBILITIES
- Develop and maintain UVM testbenches.
- Debug regressions and verification failures.
- Drive functional coverage closure and verification deliverables.
REQUIRED / PREFERRED
SystemVerilogUVMAMBA ProtocolsRegression DebugCoverage Closure
5+ years
Physical Design III
Bengaluru
Own physical-design execution from planning through tape-out, including implementation, verification, reviews and technical leadership.
CORE RESPONSIBILITIES
- Deliver fully verified physical designs at IP and top-level.
- Manage the physical-design phase from planning and requirements through tape-out.
- Own documentation, reviews, quality, progress and technical coordination.
REQUIRED / PREFERRED
CadenceVirtuosoPhysical DesignHigh Frequency / mmWaveTechnical Leadership
4+ years
DFT Engineer
Location to be confirmed
Execute DFT insertion, MBIST, JTAG, ATPG and manufacturing-test verification flows.
CORE RESPONSIBILITIES
- Hands-on MBIST and JTAG insertion.
- Pattern generation and simulation.
- RTL DFT insertion using Siemens Tessent-based flows.
REQUIRED / PREFERRED
MBISTJTAGATPGScanSiemens TessentDFT Verification
We are building the team.
AionSi is building experienced engineering teams for technically demanding semiconductor programs. Explore open roles for experienced engineers, or share your profile for future opportunities.
Bring your engineering depth.
Tell us your semiconductor discipline, experience level and the kind of engineering problems you want to work on.